1. Field of Invention
The present invention relates generally to a constant output circuit and specifically to a constant output circuit employed in an integrated circuit.
2. Description of Related Art
In Very Large Scale Integration (VLSI) chip design, certain inputs of a standard cell must be connected to a fixed-value node such as power source (logic 1) and ground (logic 0). For instance, if there are only two input signals present in a three-input NAND gate standard cell design, then the third input node needs to be preprocessed. The preprocessing can be accomplished for example, by connecting the third input to the power supply through a pull-up resistor. This example shows one of the cases that an integrated circuit designer often needs to have steady and reliable source for logic "1" and logic "0".
A circuit designer can simply use the power supply and the ground for logic "1" and logic "0" by connecting the circuit to VDD and GND respectively. Since the voltage of the power supply or the ground may deviate within a range, the VLSI chip designer often uses a constant output circuit to provide a reliable logic "1" or logic "0".
FIG. 1 is a circuit diagram of a conventional design. As shown in FIG. 1, a conventional constant output circuit comprises an inverter gate 11 and a NAND gate 12. The output 121 of NAND gate 12 is coupled to the input of inverter gate 11 and NAND gate 12; the output 111 is coupled to the other input of NAND gate 12. Output 121 of this circuit is of logic "1" and output 111 is of logic "0".
When there are noises in ground (GND) and power supply (VDD), error may occur in inverter gate 11. As a result, output 121 erroneously has a logic "0" and input 111 a logic "1". More errors may begin to occur from then on in the downstream circuits. Although the output value of the above circuit may correct itself, yet it takes up quite a long delay time, approximately 14 nanosecond (NS). FIG. 2 is a timing diagram that depicts the variation of outputs 111, 121 from incorrect output values to correct output values. The shortcoming of the above conventional constant output circuit results from the fact that the logic "1" output has both the path to the power supply (VDD) and the path to the ground (GND). Similarly, the logic "0" output has path to the power supply (VDD) and also the path to the ground (GND). Unstable voltage of the power supply or the ground may introduce error outputs of inverting gate 11, and then error output of signals 111, 121 may result.
The present invention can solve this problem by incorporating a stable constant output circuit in the circuit design. High reliability is a major feature of this invention. Since the logic "0" output does not have path to the power supply (VDD) and the logic "1" output does not have path to the ground (GND), errors resulted from the unstable voltage of the power supply or the ground will never occur in the invention.
The constant output circuit of the present invention also features a fast speed of reaching the stable state. Its operating speed is several times faster than that of the prior art.